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<h1 id="cmpt-295---unit--microprocessor-design--instruction-execution">CMPT 295 - Unit – Microprocessor Design & Instruction Execution</h1>
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<p>Lecture 26</p>
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<ul>
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<li>Intro to Logic Design</li>
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</ul>
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<h1 id="last-lecture">Last Lecture</h1>
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<ul>
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<li>ISA design
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<ul>
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<li>MIPS</li>
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<li>Created our own x295M: “Memory only”</li>
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</ul>
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</li>
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<li>ISA Evaluation
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<ul>
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<li>Examining the effect of the von Neumann bottleneck on the
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execution time of our program by counting number of
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memory accesses
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<ul>
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<li>The fewer memory accesses our program makes, the faster it
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executes, hence the “better” it is</li>
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</ul>
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</li>
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</ul>
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</li>
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<li>Improvements:
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<ul>
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<li>Decreasing effect of von Neumann bottleneck by reducing
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the number of memory accesses</li>
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</ul>
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</li>
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</ul>
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<p>And one way to achieve this is by introducing registers in the design of the ISA -> makes machine instructions shorter.
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Reducing the number of operands may also help (but not always).</p>
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<h2 id="todays-menu">Today’s Menu</h2>
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<ul>
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<li>Instruction Set Architecture (ISA)
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<ul>
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<li>Definition of ISA</li>
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</ul>
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</li>
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<li>Instruction Set design
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<ul>
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<li>Design principles</li>
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<li>Look at an example of an instruction set: MIPS</li>
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<li>Create our own</li>
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<li>ISA evaluation</li>
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</ul>
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</li>
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<li>(highlighted) Implementation of a microprocessor (CPU) based on an ISA
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<ul>
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<li>(highlighted) Execution of machine instructions (datapath)</li>
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<li>(highlighted) Intro to logic design + Combinational logic + Sequential logic circuit</li>
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<li>Sequential execution of machine instructions</li>
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<li>Pipelined execution of machine instructions + Hazards</li>
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</ul>
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</li>
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</ul>
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<h2 id="the-big-picture">The Big Picture</h2>
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<ul>
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<li>C code:
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<ul>
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<li>C Program (.c) -> sum_store.c</li>
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<li>C Preprocessor creates: Preprocessed Source -> sum_store.i</li>
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</ul>
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</li>
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<li>Assembly code:
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<ul>
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<li>C compiler creates: Assembly program (.s) -> sum_store.s</li>
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</ul>
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</li>
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<li>Machine code:
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<ul>
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<li>Linker grates: Object (.o) -> sum_store.o</li>
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</ul>
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</li>
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<li>ISA - Instruction Set Architecture: An agreement establishing how software communicates with CPU.
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<ul>
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<li>Loader creates: Executable -> ss</li>
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<li>Computer executed it
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<ul>
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<li>CPU</li>
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<li>Memory</li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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<p>Now that we have had a
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look at a few instruction
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set architectures (ISA), i.e.,</p>
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<ul>
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<li>Specification of various
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models (memory model,
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computational model,
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operand model, etc … ),
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and …</li>
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<li>Design of instruction set (or
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subset) (assembly
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instructions and their
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corresponding machine
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instructions, their formats,
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etc. ) …</li>
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</ul>
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<p>… let’s step over this
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interface and explore
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how the microprocessor is
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constructed so it can
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execute these machine
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4 instructions</p>
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<h2 id="datapath-of-a-mips-microprocessor">Datapath of a MIPS microprocessor</h2>
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<p>Sneak preview (how CPU hardware updates
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the PC in fetch-decode-execute loop):
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0x00400000
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(from our Lecture 25)</p>
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<ul>
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<li>Consider the memory address
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0x00400000 i.e.,
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<code class="language-plaintext highlighter-rouge">0000 0000 0100 0000 0000 0000 0000 0000</code>
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which holds the MIPS machine instruction
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<code class="language-plaintext highlighter-rouge">100011 11101 10001 0000000000000000</code></li>
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<li>PC contains 0x00400000 i.e.,
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32 line bus with signals 0x00400000 input
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into ADDER with “4” as other input</li>
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<li>ADDER adds both inputs and produces
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0x00400004 i.e., memory address of
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next machine instruction which holds
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the MIPS machine instruction
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<code class="language-plaintext highlighter-rouge">100011 11101 10010 0000000000000100</code> 32 line bus with signal 0x00400004 input into
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PC overwriting 0x00400000</li>
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</ul>
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<p>See <a href="./micro_graph.html">micro_graph.html</a></p>
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<p>Source: Page 246 in Patterson and Hennessy</p>
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<h2 id="digital-circuits">Digital circuits</h2>
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<ul>
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<li>In order to understand how the microprocessor executes these machine instructions (series of 0’s and 1’s), we need to have a look at the components of a microprocessor and how they function: Types of components found in a digital system such as a microprocessor
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<ol>
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<li>Combinational logic -> manipulate bits (compute functions on
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bits e.g., ADD)</li>
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<li>Memory elements -> store bits</li>
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<li>Clock signals -> regulate the update of memory elements</li>
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</ol>
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</li>
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<li>And what affects the execution speed of these components
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such as propagation delay</li>
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<li>So, we need to understand a few things about digital circuits</li>
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</ul>
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<h2 id="microprocessor">Microprocessor</h2>
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<ul>
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<li>Made of resistors,
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capacitors, diodes,
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and transistors</li>
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<li>For example, 10-core Core i7
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Broadwell-E (2016) from Intel
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contains 3,200,000,000 transistors
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Source: <a href="https://en.wikipedia.org/wiki/Transistor_count">https://en.wikipedia.org/wiki/Transistor_count</a></li>
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<li>Lots of incredibly small components</li>
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</ul>
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<p>Source: <a href="https://www.newegg.ca/Product/Product.aspx">https://www.newegg.ca/Product/Product.aspx</a></p>
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<p>Source: <a href="https://www.elprocus.com/semiconductor-devices-types-and-applications">https://www.elprocus.com/semiconductor-devices-types-and-applications</a></p>
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<h2 id="logic-gates">Logic gates</h2>
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<ul>
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<li>Definition: A logic gate is an
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electronic device that can
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perform a Boolean function
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(AND, NAND, OR, XOR, NOT)</li>
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<li>On a chip, these can be
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made using transistors,
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resistors, and diodes</li>
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<li>Here is how a NOT logic gate
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is constructed:</li>
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</ul>
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<p>(Transcriber’s note: I’m sorry but I have no fucking idea how to transcribe this diagram.
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It is <em>way</em> too complex to describe with plain text,
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and contains special symbols for electrical components I don’t recognize.)</p>
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<p>Source: <a href="http://www.cybermike.net/reference/liec_book/Digital/DIGI_3.html">http://www.cybermike.net/reference/liec_book/Digital/DIGI_3.html</a></p>
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<p>from Quora: 2.5 transistors/logic gate ∴ 640 millions [sic] to ~2 billions [sic] logic gate on 1 microprocessor!</p>
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<h2 id="behaviour-of-logic-gates">Behaviour of logic gates</h2>
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<ul>
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<li>Here is a diagram representing
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the behaviour of an AND logic…both switches must be closed.
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<ul>
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<li>A positive and negative terminal are connected to a lamp. On the positive side, between the terminal and the lamp are two gates in series. They are labeled A and B. They are both open. This means they are not connected to the wire.</li>
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</ul>
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</li>
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<li>Here is a diagram representing
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the behaviour of an OR logic…either (or both) switch must be closed!</li>
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<li>A positive and negative terminal are connected to a lamp. On the positive side, between the terminal and the lamp are two gates in parallel, where the line splits in two. They are labeled A and B. They are both open. This means they are not connected to the wire.</li>
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</ul>
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<p><a href="https://www.electronics-tutorials.ws/boolean/bool_1.html">https://www.electronics-tutorials.ws/boolean/bool_1.html</a></p>
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<p><a href="https://www.electronics-tutorials.ws/boolean/bool_2.html">https://www.electronics-tutorials.ws/boolean/bool_2.html</a></p>
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<h2 id="abstracting-using-black-boxes">Abstracting using black boxes</h2>
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<ul>
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<li>A black box is used to abstract the function of a device
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<ul>
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<li>The input and output of the device are visible/known
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<ul>
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<li>The idea is that we need to know these in order to use
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the device</li>
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</ul>
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</li>
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<li>The implementation of the devide (what is inside) is
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invisible/unknown, i.e., hidden
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<ul>
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<li>The idea is that we do not need to know how the
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device is implemented in order to use it</li>
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</ul>
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</li>
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</ul>
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</li>
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<li>Same thing is true for functions in software!</li>
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</ul>
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<h2 id="abstracting-logic-gates">Abstracting logic gates</h2>
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<ul>
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<li>Instead of drawing logic gates using their electronic components,
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we hide these components using a black box -> a symbol
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simplified representing a logic gate</li>
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<li>Symbols:
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<ul>
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<li>AND
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<ul>
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<li>Inputs: A, B</li>
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<li>Outputs: AB</li>
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</ul>
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</li>
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<li>OR
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<ul>
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<li>Inputs: A, B</li>
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<li>Outputs: A+B</li>
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</ul>
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</li>
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<li>XOR
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<ul>
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<li>Inputs: A, B</li>
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<li>Outputs: A⊕B</li>
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</ul>
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</li>
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</ul>
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</li>
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<li>Input: a signal i.e., 0 or 1 (abstraction of voltage levels) travels
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along the input wire/line</li>
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<li>Output: After a time delay (propagation delay tpd), a signal, i.e., 0
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or 1 travels along the output wire/line</li>
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<li>Always active
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<ul>
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<li>As soon as signal (0 or 1) travels along the input wires/lines, the
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logical gate produces a result, i.e., a signal (0 or 1) which then travels
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along the output wire/line</li>
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</ul>
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</li>
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</ul>
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<h2 id="abstracting-logic-gates--contd">Abstracting logic gates – cont’d</h2>
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<p>(Annotation: Homework: Label input & output line.)</p>
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<ul>
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<li>Symbols:
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<ul>
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<li>NAND
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<ul>
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<li>Inputs: A, B</li>
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<li>Outputs: <span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><mover accent="true"><mrow><mi>A</mi><mi>B</mi></mrow><mo stretchy="true">‾</mo></mover></mrow><annotation encoding="application/x-tex">\overline{AB}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.8833300000000001em;vertical-align:0em;"></span><span class="mord overline"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.8833300000000001em;"><span style="top:-3em;"><span class="pstrut" style="height:3em;"></span><span class="mord"><span class="mord mathnormal">A</span><span class="mord mathnormal" style="margin-right:0.05017em;">B</span></span></span><span style="top:-3.80333em;"><span class="pstrut" style="height:3em;"></span><span class="overline-line" style="border-bottom-width:0.04em;"></span></span></span></span></span></span></span></span></span></li>
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</ul>
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</li>
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<li>NOT (inverter)
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<ul>
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<li>Inputs: A</li>
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<li>Outputs: <span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><mover accent="true"><mi>A</mi><mo stretchy="true">‾</mo></mover></mrow><annotation encoding="application/x-tex">\overline{A}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.8833300000000001em;vertical-align:0em;"></span><span class="mord overline"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.8833300000000001em;"><span style="top:-3em;"><span class="pstrut" style="height:3em;"></span><span class="mord"><span class="mord mathnormal">A</span></span></span><span style="top:-3.80333em;"><span class="pstrut" style="height:3em;"></span><span class="overline-line" style="border-bottom-width:0.04em;"></span></span></span></span></span></span></span></span></span></li>
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</ul>
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</li>
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<li>NOR
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<ul>
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<li>Inputs: A, B</li>
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<li>Outputs: <span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><mover accent="true"><mrow><mi>A</mi><mo>+</mo><mi>B</mi></mrow><mo stretchy="true">‾</mo></mover></mrow><annotation encoding="application/x-tex">\overline{A+B}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.9666600000000001em;vertical-align:-0.08333em;"></span><span class="mord overline"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.8833300000000001em;"><span style="top:-3em;"><span class="pstrut" style="height:3em;"></span><span class="mord"><span class="mord mathnormal">A</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">+</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mord mathnormal" style="margin-right:0.05017em;">B</span></span></span><span style="top:-3.80333em;"><span class="pstrut" style="height:3em;"></span><span class="overline-line" style="border-bottom-width:0.04em;"></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.08333em;"><span></span></span></span></span></span></span></span></span></li>
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</ul>
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</li>
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<li>BUFFER
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<ul>
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<li>Inputs: A</li>
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<li>Outputs: A</li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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<p>Purpose of buffer gate: to buffer and/or delay and/or strengthen a signal</p>
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<h2 id="propagation-delay-t_textpd">Propagation delay <span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><msub><mi>t</mi><mtext>pd</mtext></msub></mrow><annotation encoding="application/x-tex">t_{\text{pd}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.9011879999999999em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathnormal">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.3361079999999999em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord text mtight"><span class="mord mtight">pd</span></span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span></span></span></span></h2>
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<ul>
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<li>Definition: Longest time elapsed between the
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application of an input and the occurrence of the
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corresponding output</li>
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<li><span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><msub><mi>t</mi><mtext>pd</mtext></msub></mrow><annotation encoding="application/x-tex">t_{\text{pd}}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.9011879999999999em;vertical-align:-0.286108em;"></span><span class="mord"><span class="mord mathnormal">t</span><span class="msupsub"><span class="vlist-t vlist-t2"><span class="vlist-r"><span class="vlist" style="height:0.3361079999999999em;"><span style="top:-2.5500000000000003em;margin-left:0em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord text mtight"><span class="mord mtight">pd</span></span></span></span></span></span><span class="vlist-s"></span></span><span class="vlist-r"><span class="vlist" style="height:0.286108em;"><span></span></span></span></span></span></span></span></span></span> often expressed in picosecond (<span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><mn>1</mn><msup><mn>0</mn><mrow><mo>−</mo><mn>12</mn></mrow></msup></mrow><annotation encoding="application/x-tex">10^{-12}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.8141079999999999em;vertical-align:0em;"></span><span class="mord">1</span><span class="mord"><span class="mord">0</span><span class="msupsub"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.8141079999999999em;"><span style="top:-3.063em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mtight">−</span><span class="mord mtight">12</span></span></span></span></span></span></span></span></span></span></span></span> seconds)
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to nanosecond (<span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><mn>1</mn><msup><mn>0</mn><mrow><mo>−</mo><mn>9</mn></mrow></msup></mrow><annotation encoding="application/x-tex">10^{-9}</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.8141079999999999em;vertical-align:0em;"></span><span class="mord">1</span><span class="mord"><span class="mord">0</span><span class="msupsub"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.8141079999999999em;"><span style="top:-3.063em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mtight">−</span><span class="mord mtight">9</span></span></span></span></span></span></span></span></span></span></span></span> seconds)</li>
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</ul>
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<h2 id="summary">Summary</h2>
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<ul>
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<li>We have now started to explore how the microprocessor
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executes machine instructions (series of 0’s and 1’s)
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<ul>
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<li>More specifically, how its datapath can be constructed</li>
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</ul>
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</li>
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<li>Microprocessor itself is …
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<ul>
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<li>Made of resistors, capacitors, diodes, and transistors</li>
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<li>Billions of them, so understanding their behaviours (what they
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do) once they are linked together is too onerous</li>
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<li>So we resort to abstraction (black box) in order to understand
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their functioning
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<ul>
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<li>Logic gates: perform a Boolean function</li>
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</ul>
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</li>
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<li>Hardware components (i.e., logic gates) have propagation
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delay
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<ul>
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<li>Signals (0’s and 1’s) take time to propagate through them</li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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<h2 id="next-lecture">Next Lecture</h2>
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<ul>
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<li>Instruction Set Architecture (ISA)
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<ul>
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<li>Definition of ISA</li>
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</ul>
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</li>
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<li>Instruction Set design
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<ul>
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<li>Design principles</li>
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<li>Look at an example of an instruction set: MIPS</li>
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<li>Create our own</li>
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<li>ISA evaluation</li>
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</ul>
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</li>
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<li>(highlighted) Implementation of a microprocessor (CPU) based on an ISA
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<ul>
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<li>(highlighted) Execution of machine instructions (datapath)</li>
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<li>(highlighted) Intro to logic design + Combinational logic + Sequential logic circuit</li>
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<li>Sequential execution of machine instructions</li>
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<li>Pipelined execution of machine instructions + Hazards</li>
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</ul>
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</li>
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</ul>
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<footer>
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</footer>
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</div>
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</main>
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</body>
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</html>
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