CMPT 295 - Unit – Microprocessor Design & Instruction Execution
Lecture 26
- Intro to Logic Design
Last Lecture
- ISA design
- MIPS
- Created our own x295M: “Memory only”
- ISA Evaluation
- Examining the effect of the von Neumann bottleneck on the
execution time of our program by counting number of
memory accesses
- The fewer memory accesses our program makes, the faster it executes, hence the “better” it is
- Examining the effect of the von Neumann bottleneck on the
execution time of our program by counting number of
memory accesses
- Improvements:
- Decreasing effect of von Neumann bottleneck by reducing the number of memory accesses
And one way to achieve this is by introducing registers in the design of the ISA -> makes machine instructions shorter. Reducing the number of operands may also help (but not always).
Today’s Menu
- Instruction Set Architecture (ISA)
- Definition of ISA
- Instruction Set design
- Design principles
- Look at an example of an instruction set: MIPS
- Create our own
- ISA evaluation
- (highlighted) Implementation of a microprocessor (CPU) based on an ISA
- (highlighted) Execution of machine instructions (datapath)
- (highlighted) Intro to logic design + Combinational logic + Sequential logic circuit
- Sequential execution of machine instructions
- Pipelined execution of machine instructions + Hazards
The Big Picture
- C code:
- C Program (.c) -> sum_store.c
- C Preprocessor creates: Preprocessed Source -> sum_store.i
- Assembly code:
- C compiler creates: Assembly program (.s) -> sum_store.s
- Machine code:
- Linker grates: Object (.o) -> sum_store.o
- ISA - Instruction Set Architecture: An agreement establishing how software communicates with CPU.
- Loader creates: Executable -> ss
- Computer executed it
- CPU
- Memory
Now that we have had a look at a few instruction set architectures (ISA), i.e.,
- Specification of various models (memory model, computational model, operand model, etc … ), and …
- Design of instruction set (or subset) (assembly instructions and their corresponding machine instructions, their formats, etc. ) …
… let’s step over this interface and explore how the microprocessor is constructed so it can execute these machine 4 instructions
Datapath of a MIPS microprocessor
Sneak preview (how CPU hardware updates the PC in fetch-decode-execute loop): 0x00400000 (from our Lecture 25)
- Consider the memory address
0x00400000 i.e.,
0000 0000 0100 0000 0000 0000 0000 0000
which holds the MIPS machine instruction100011 11101 10001 0000000000000000
- PC contains 0x00400000 i.e., 32 line bus with signals 0x00400000 input into ADDER with “4” as other input
- ADDER adds both inputs and produces
0x00400004 i.e., memory address of
next machine instruction which holds
the MIPS machine instruction
100011 11101 10010 0000000000000100
32 line bus with signal 0x00400004 input into PC overwriting 0x00400000
See micro_graph.html
Source: Page 246 in Patterson and Hennessy
Digital circuits
- In order to understand how the microprocessor executes these machine instructions (series of 0’s and 1’s), we need to have a look at the components of a microprocessor and how they function: Types of components found in a digital system such as a microprocessor
- Combinational logic -> manipulate bits (compute functions on bits e.g., ADD)
- Memory elements -> store bits
- Clock signals -> regulate the update of memory elements
- And what affects the execution speed of these components such as propagation delay
- So, we need to understand a few things about digital circuits
Microprocessor
- Made of resistors, capacitors, diodes, and transistors
- For example, 10-core Core i7 Broadwell-E (2016) from Intel contains 3,200,000,000 transistors Source: https://en.wikipedia.org/wiki/Transistor_count
- Lots of incredibly small components
Source: https://www.newegg.ca/Product/Product.aspx
Source: https://www.elprocus.com/semiconductor-devices-types-and-applications
Logic gates
- Definition: A logic gate is an electronic device that can perform a Boolean function (AND, NAND, OR, XOR, NOT)
- On a chip, these can be made using transistors, resistors, and diodes
- Here is how a NOT logic gate is constructed:
(Transcriber’s note: I’m sorry but I have no fucking idea how to transcribe this diagram. It is way too complex to describe with plain text, and contains special symbols for electrical components I don’t recognize.)
Source: http://www.cybermike.net/reference/liec_book/Digital/DIGI_3.html
from Quora: 2.5 transistors/logic gate ∴ 640 millions [sic] to ~2 billions [sic] logic gate on 1 microprocessor!
Behaviour of logic gates
- Here is a diagram representing
the behaviour of an AND logic…both switches must be closed.
- A positive and negative terminal are connected to a lamp. On the positive side, between the terminal and the lamp are two gates in series. They are labeled A and B. They are both open. This means they are not connected to the wire.
- Here is a diagram representing the behaviour of an OR logic…either (or both) switch must be closed!
- A positive and negative terminal are connected to a lamp. On the positive side, between the terminal and the lamp are two gates in parallel, where the line splits in two. They are labeled A and B. They are both open. This means they are not connected to the wire.
https://www.electronics-tutorials.ws/boolean/bool_1.html
https://www.electronics-tutorials.ws/boolean/bool_2.html
Abstracting using black boxes
- A black box is used to abstract the function of a device
- The input and output of the device are visible/known
- The idea is that we need to know these in order to use the device
- The implementation of the devide (what is inside) is
invisible/unknown, i.e., hidden
- The idea is that we do not need to know how the device is implemented in order to use it
- The input and output of the device are visible/known
- Same thing is true for functions in software!
Abstracting logic gates
- Instead of drawing logic gates using their electronic components, we hide these components using a black box -> a symbol simplified representing a logic gate
- Symbols:
- AND
- Inputs: A, B
- Outputs: AB
- OR
- Inputs: A, B
- Outputs: A+B
- XOR
- Inputs: A, B
- Outputs: A⊕B
- AND
- Input: a signal i.e., 0 or 1 (abstraction of voltage levels) travels along the input wire/line
- Output: After a time delay (propagation delay tpd), a signal, i.e., 0 or 1 travels along the output wire/line
- Always active
- As soon as signal (0 or 1) travels along the input wires/lines, the logical gate produces a result, i.e., a signal (0 or 1) which then travels along the output wire/line
Abstracting logic gates – cont’d
(Annotation: Homework: Label input & output line.)
- Symbols:
- NAND
- Inputs: A, B
- Outputs:
- NOT (inverter)
- Inputs: A
- Outputs:
- NOR
- Inputs: A, B
- Outputs:
- BUFFER
- Inputs: A
- Outputs: A
- NAND
Purpose of buffer gate: to buffer and/or delay and/or strengthen a signal
Propagation delay
- Definition: Longest time elapsed between the application of an input and the occurrence of the corresponding output
- often expressed in picosecond ( seconds) to nanosecond ( seconds)
Summary
- We have now started to explore how the microprocessor
executes machine instructions (series of 0’s and 1’s)
- More specifically, how its datapath can be constructed
- Microprocessor itself is …
- Made of resistors, capacitors, diodes, and transistors
- Billions of them, so understanding their behaviours (what they do) once they are linked together is too onerous
- So we resort to abstraction (black box) in order to understand
their functioning
- Logic gates: perform a Boolean function
- Hardware components (i.e., logic gates) have propagation
delay
- Signals (0’s and 1’s) take time to propagate through them
Next Lecture
- Instruction Set Architecture (ISA)
- Definition of ISA
- Instruction Set design
- Design principles
- Look at an example of an instruction set: MIPS
- Create our own
- ISA evaluation
- (highlighted) Implementation of a microprocessor (CPU) based on an ISA
- (highlighted) Execution of machine instructions (datapath)
- (highlighted) Intro to logic design + Combinational logic + Sequential logic circuit
- Sequential execution of machine instructions
- Pipelined execution of machine instructions + Hazards