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81 lines
1.3 KiB
81 lines
1.3 KiB
[
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{
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"name": "PC",
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"short_name": "pc",
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"cons": ["add1", "addr"]
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},
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{
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"name": "Add (1)",
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"short_name": "add1",
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"cons": ["add2"]
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},
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{
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"name": "4",
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"short_name": "4",
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"cons": ["add1"]
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},
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{
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"name": "Add (2)",
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"short_name": "add2",
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"cons": ["pc"]
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},
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{
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"name": "Instruction memory",
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"short_name": "insmem",
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"subitems": [
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{
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"name": "Address",
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"short_name": "addr"
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},
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{
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"name": "Insturction",
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"short_name": "instr",
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"cons": ["reg1", "reg2", "reg3", "alu"]
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}
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]
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},
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{
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"name": "Registers",
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"short_name": "regs",
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"cons": ["alu", "alu", "data2"],
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"subitems": [
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{
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"name": "Data",
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"short_name": "data"
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},
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{
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"name": "Register #1",
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"short_name": "reg1"
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},
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{
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"name": "Register #2",
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"short_name": "reg2"
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},
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{
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"name": "Register #3",
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"short_name": "reg3"
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}
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]
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},
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{
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"name": "ALU",
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"short_name": "alu",
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"cons": ["add2", "data"]
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},
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{
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"name": "Data Memory",
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"short_name": "datamem",
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"cons": ["data"],
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"subitems": [
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{
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"name": "Address",
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"short_name": "addr2"
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},
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{
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"name": "Data",
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"short_name": "data2"
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}
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]
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}
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]
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