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<h1 id="assignment-7---cmpt-295--fall-2021">Assignment 7 - CMPT 295 – Fall 2021</h1>
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<h2 id="objectives">Objectives:</h2>
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<ul>
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<li>Designing and evaluating instruction sets (ISA)</li>
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</ul>
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<hr />
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<h2 id="submission">Submission:</h2>
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<ul>
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<li>Submit your document called Assignment_7.pdf, which must include your answers to all
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of the questions in Assignment 7.
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<ul>
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<li>Add your full name and student number at the top of the first page of your
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document Assignment_7.pdf.</li>
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</ul>
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</li>
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<li>Submit your assignment Assignment_7.pdf on CourSys.</li>
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</ul>
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<hr />
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<h2 id="due">Due:</h2>
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<ul>
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<li>Friday Nov. 12 at 23:59:59.</li>
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<li>Late assignments will receive a grade of 0, but they will be marked (if they are submitted
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before the solutions are posted on Monday) in order to provide feedback to the
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student.</li>
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</ul>
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<hr />
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<h2 id="marking-scheme">Marking scheme:</h2>
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<ul>
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<li>The marks assigned to each question is indicated in [ ].</li>
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<li>This assignment will be marked for correctness.</li>
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<li>A solution will be posted on Monday after the due date.</li>
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</ul>
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<hr />
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<p>Note: In our lectures, we designed and evaluated the instruction set called x295M. In this
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assignment, we shall design and evaluate three (3) other instruction sets: x295, x295+
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and x295++.</p>
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<p>Be aware: All of these 4 instruction sets are different!</p>
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<hr />
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<h2 id="instruction-set-1--x295">Instruction Set 1 – x295</h2>
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<h3 id="a-description-of-x295-instruction-set-architecture-isa">A. Description of x295 instruction set architecture (ISA)</h3>
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<ul>
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<li>Data type size : 16 bits (for example, an integer has 16 bits)</li>
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<li>Memory model
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<ul>
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<li>Size of memory: <span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><msup><mn>2</mn><mn>12</mn></msup><mo>×</mo><mn>16</mn></mrow><annotation encoding="application/x-tex">2^{12} \times 16</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.897438em;vertical-align:-0.08333em;"></span><span class="mord"><span class="mord">2</span><span class="msupsub"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.8141079999999999em;"><span style="top:-3.063em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight"><span class="mord mtight">12</span></span></span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2222222222222222em;"></span><span class="mbin">×</span><span class="mspace" style="margin-right:0.2222222222222222em;"></span></span><span class="base"><span class="strut" style="height:0.64444em;vertical-align:0em;"></span><span class="mord">16</span></span></span></span>
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<ul>
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<li>m = 12 -> this means that each memory address has 12 bits.</li>
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<li>n = 16 -> this means that the address resolution, i.e., the smallest
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addressable memory “chunk”, is a memory “chunk” of 16 bits.
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<ul>
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<li>Each memory “chunk” of 16 bits has a distinct memory address.</li>
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<li>This is not a byte-addressable computer</li>
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</ul>
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</li>
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</ul>
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</li>
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<li>Word size: 16 bits -> this means that when the microprocessor reads from/writes
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to memory, it reads/writes 16 bits at a time.
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<ul>
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<li>In this ISA, the address resolution == the word size. It is not always the case.</li>
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</ul>
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</li>
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<li>Number of registers: 0</li>
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</ul>
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</li>
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<li>Instruction set (assembly and machine instructions)
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<ul>
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<li>Maximum number of instructions: 16
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<ul>
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<li>This means that we need a maximum of 4 bits to distinctly represent each
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of these 16 instructions.</li>
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<li>Therefore, the size of the opcode field, in the machine instructions, will be
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4 bits (<span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><msup><mn>2</mn><mn>4</mn></msup><mo>=</mo><mn>16</mn></mrow><annotation encoding="application/x-tex">2^4 = 16</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.8141079999999999em;vertical-align:0em;"></span><span class="mord"><span class="mord">2</span><span class="msupsub"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.8141079999999999em;"><span style="top:-3.063em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight">4</span></span></span></span></span></span></span></span><span class="mspace" style="margin-right:0.2777777777777778em;"></span><span class="mrel">=</span><span class="mspace" style="margin-right:0.2777777777777778em;"></span></span><span class="base"><span class="strut" style="height:0.64444em;vertical-align:0em;"></span><span class="mord">16</span></span></span></span>)</li>
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</ul>
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</li>
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<li>Operand Model:
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<ul>
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<li>Memory (only) – only memory locations are operands, no registers are
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used as operands except the register representing the stack pointer</li>
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<li>3-operand model</li>
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<li>In the machine instructions, the order of these operands is: Dest, Src1, Src2</li>
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</ul>
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</li>
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<li>Memory addressing mode: Direct, Base and Displacement and Indirect
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<ul>
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<li>These may not all be used in the instructions found in this assignment.</li>
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</ul>
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</li>
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<li>Assembly instructions (in this assignment we shall only define a subset of these
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instructions) and their format and meaning:
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<ul>
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<li><code class="language-plaintext highlighter-rouge">ADD a,b,c</code>; meaning: <code class="language-plaintext highlighter-rouge">M[c] <- M[a] + M[b]</code></li>
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<li><code class="language-plaintext highlighter-rouge">SUB a,b,c</code>; meaning: <code class="language-plaintext highlighter-rouge">M[c] <- M[a] - M[b]</code></li>
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<li><code class="language-plaintext highlighter-rouge">MUL a,b,c</code>; meaning: <code class="language-plaintext highlighter-rouge">M[c] <- M[a] * M[b]</code></li>
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<li>In these assembly instructions, the order of the operands is: Src1, Src2,
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Dest.</li>
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</ul>
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</li>
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<li>Machine code format:
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opcode
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<ul>
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<li>
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<table>
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<thead>
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<tr>
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<th>label</th>
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<th>bits</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>opcode</td>
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<td>4</td>
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</tr>
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<tr>
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<td>dest</td>
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<td>12</td>
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</tr>
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<tr>
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<td>padding</td>
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<td>4</td>
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</tr>
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<tr>
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<td>src</td>
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<td>12</td>
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</tr>
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<tr>
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<td>padding</td>
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<td>4</td>
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</tr>
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<tr>
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<td>src2</td>
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<td>12</td>
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</tr>
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</tbody>
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</table>
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</li>
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<li>This format is made of 3 words, each word is 16 bits in length (word size). This
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format must be used to form all three machine instructions corresponding to the
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three assembly instructions listed above.
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The bit patterns for the opcode are:
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<ul>
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<li>
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<table>
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<thead>
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<tr>
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<th>Opcode (instruction)</th>
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<th>bit pattern (4 bits)</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>padding</td>
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<td>0000</td>
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</tr>
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<tr>
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<td>ADD</td>
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<td>0001</td>
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</tr>
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<tr>
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<td>SUB</td>
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<td>0010</td>
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</tr>
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<tr>
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<td>MUL</td>
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<td>0011</td>
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</tr>
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<tr>
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<td>…</td>
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<td>…</td>
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</tr>
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</tbody>
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</table>
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</li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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<h3 id="b-evaluation-of-x295-instruction-set">B. Evaluation of x295 instruction set</h3>
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<table>
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<thead>
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<tr>
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<th>C program</th>
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<th>x295 assembly program</th>
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<th>x295 machine code</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td><pre>z = (x + y) * (x - y);</pre></td>
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<td><pre>ADD x,y,tmp1
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SUB x,y,imp2
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MUL tmp1,tmp2,z</pre> (where tmp1 and tmp2 are memory addresses for holding temporary resylts)</td>
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<td><pre>0001 <Dest 12 bits>
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0000 <Src1 12 bits>
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0000 <Src2 12 bits>
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0011 <Dest 12 bits>
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0000 <Src1 12 bits>
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0000 <Src2 12 bits>
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</pre>
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Note: in the above machine code, we arbitarily express the memory address as `<Dest 12 bits>`, `<Src1 12 bits>` and `<Src2 12 bits>` as opposed to using actual memory addresses in the memory address fields (fields in between < and >).
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</td>
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</tr>
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</tbody>
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</table>
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<p>1) The first step in evaluating our x295 instruction set is to write an assembly program using
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the assembly instructions defined by our x295 instruction set. This step has been done
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for us and is displayed in the table above in column “x295 assembly program”.</p>
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<p>Note that as we are performing this step, we are verifying that our x295 instruction set
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contains sufficient instructions to allow us to write such program in x295 assembly code.</p>
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<p>(There is nothing for us to do in this part of our x295 instruction set evaluation. We can
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use this as a model to follow when answering the rest of this assignment.)</p>
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<p>Once we have our x295 assembly program, we need to transform it into its x295
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machine code equivalent. This step has been done for us and is displayed in the table
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above in column “x295 machine code”.</p>
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<p>Note that as we are performing this step, we are verifying that our x295 instruction set
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contains sufficient instructions to allow us to write such program in x295 machine code.</p>
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<p>(Again, there is nothing for us to do in this part of our x295 instruction set evaluation.
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We can use this as a model to follow when answering the rest of this assignment.)</p>
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<p>2) The next step is evaluating our x295 instruction set is to execute (hand trace) our
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assembly program or its corresponding machine code and using the metric (criteria) called
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memory traffic, we count the number of memory accesses our program makes during its
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execution. In other words, we count how many time the execution of our program
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required a word (16 bits) to be read from or written to memory.</p>
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<p>Note that as we are performing this step, we are verifying that the meaning of the
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instructions contained in our x295 instruction set is such that hand tracing these
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instructions does indeed produce the result the software developer that wrote the above
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C program expected. This is to say that if we use the test case: x = 3, y = 2 when hand
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tracing our x295 assembly code (or its machine code equivalent), we would obtain the
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same (expected) result as if we were to hand trace the C program itself.</p>
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<p>For us to do: As part of this step in the evaluation of our x295 instruction set, we are
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asked to evaluate the number of word size memory accesses made by the
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microprocessor when it is fetching and decoding/executing each assembly code
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statement (or machine code statement) listed in the left column in the table below. Also
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we need to justify our count. Finally, let’s total our counts. [2 marks]</p>
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<table>
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<thead>
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<tr>
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<th>x295 program (in machine language and assembly code)</th>
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<th>Fetch (number of word size memory accessors) + Provide an expaination explaining the count</th>
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<th>Decode/Execute (number of word size memory accessors) + Provide an explaination explaining the count</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td><pre>ADD x,y,tmp1</pre>
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<br />
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<pre>0001 <Dest 12 bits>
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0000 <Src1 12 bits>
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0000 <Src2 12 bits></pre></td>
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<td>Count: ____<br />
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Explaination: ____</td>
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<td>Count: ____<br />
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Explaination: ____</td>
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</tr>
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<tr>
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<td><pre>SUB x,y,tmp2</pre>
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<br />
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<pre>0010 <Dest 12 bits>
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0000 <Src1 12 bits>
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0000 <Src2 12 bits></pre></td>
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<td>Count: ____<br />
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Explaination: ____</td>
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<td>Count: ____<br />
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Explaination: ____</td>
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</tr>
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<tr>
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<td><pre>MUL tmp1,tmp2,z</pre>
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<br />
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<pre>0011 <Dest 12 bits>
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0000 <Src1 12 bits>
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0000 <Src2 12 bits></pre></td>
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<td>Count: ____<br />
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Explaination: ____</td>
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<td>Count: ____<br />
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Explaination: ____</td>
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</tr>
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<tr>
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<td>Grand total: ____</td>
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<td>Total: ____</td>
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<td>Total: ____</td>
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</tr>
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</tbody>
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</table>
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<p>3) We also evaluate our instruction set using the metric (criteria) called static code size:</p>
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<ul>
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<li>The code size of our x295 program is 3 instructions.</li>
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<li>And since each instruction is 3 word long, the code size of our x295 program is 9
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words.</li>
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</ul>
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<p>(There is nothing for us to do in this part of our x295 instruction set evaluation. We can
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use this as a model to follow when answering the rest of this assignment.)</p>
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<hr />
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<h2 id="instruction-set-2--x295">Instruction Set 2 – x295+</h2>
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<h3 id="a-description-of-x295-instruction-set-architecture-isa-1">A. Description of x295+ instruction set architecture (ISA)</h3>
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<p>Considering the results of our x295 instruction set evaluation, one possible improvement in
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order to reduce the number of memory accesses could be to reduce the size of the machine
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instructions. Since these are made of an opcode and a memory address, we could introduce
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registers which could hold these memory addresses and take less space in the machine code
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than memory addresses (i.e., registers will take fewer bits to identify than memory addresses).</p>
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<p>With the idea of introducing registers, we specified a second instruction set architecture (ISA)
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with the same components as x295, but with the following modifications:</p>
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<ul>
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<li>Memory model
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<ul>
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<li>Number of registers: 8 x 16-bit registers
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<ul>
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<li>This means that we need a maximum of 3 bits to distinctly represent each
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of these 8 (<span class="katex"><span class="katex-mathml"><math xmlns="http://www.w3.org/1998/Math/MathML"><semantics><mrow><msup><mn>2</mn><mn>3</mn></msup></mrow><annotation encoding="application/x-tex">2^3</annotation></semantics></math></span><span class="katex-html" aria-hidden="true"><span class="base"><span class="strut" style="height:0.8141079999999999em;vertical-align:0em;"></span><span class="mord"><span class="mord">2</span><span class="msupsub"><span class="vlist-t"><span class="vlist-r"><span class="vlist" style="height:0.8141079999999999em;"><span style="top:-3.063em;margin-right:0.05em;"><span class="pstrut" style="height:2.7em;"></span><span class="sizing reset-size6 size3 mtight"><span class="mord mtight">3</span></span></span></span></span></span></span></span></span></span></span>) registers.</li>
|
|
|
<li>Therefore, the size of any register field, in the machine instructions, will be
|
|
|
3 bits in length.</li>
|
|
|
<li>Each register contains 16 bits.</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
<li>The bit patterns to uniquely identify each the registers are:
|
|
|
<ul>
|
|
|
<li>
|
|
|
<table>
|
|
|
<thead>
|
|
|
<tr>
|
|
|
<th>Register</th>
|
|
|
<th>Bit pattern (3 bits)</th>
|
|
|
</tr>
|
|
|
</thead>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td>r0</td>
|
|
|
<td>000</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>r1</td>
|
|
|
<td>001</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>r2</td>
|
|
|
<td>010</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>r3</td>
|
|
|
<td>011</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>r4</td>
|
|
|
<td>100</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>r5</td>
|
|
|
<td>101</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>r6</td>
|
|
|
<td>110</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>r7</td>
|
|
|
<td>111</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
<li>Instruction set (assembly and machine instructions)
|
|
|
<ul>
|
|
|
<li>Operand Model:
|
|
|
<ul>
|
|
|
<li>Registers</li>
|
|
|
<li>We shall also use memory addresses</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
<li>Assembly instructions:
|
|
|
<ul>
|
|
|
<li><code class="language-plaintext highlighter-rouge">ADD rA,rB,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- rA + rB</code></li>
|
|
|
<li><code class="language-plaintext highlighter-rouge">SUB rA,rB,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- rA - rB</code></li>
|
|
|
<li><code class="language-plaintext highlighter-rouge">MUL rA,rB,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- rA * rB</code></li>
|
|
|
<li><code class="language-plaintext highlighter-rouge">LOAD a,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- M[a]</code></li>
|
|
|
<li><code class="language-plaintext highlighter-rouge">STORE rA,c</code>; meaning: <code class="language-plaintext highlighter-rouge">M[c] <- rA</code></li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
<li>Machine code format:
|
|
|
<ul>
|
|
|
<li>Format 1:
|
|
|
<ul>
|
|
|
<li>
|
|
|
<table>
|
|
|
<thead>
|
|
|
<tr>
|
|
|
<th>Label</th>
|
|
|
<th>Bits</th>
|
|
|
</tr>
|
|
|
</thead>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td>Opcode</td>
|
|
|
<td>4 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Dest</td>
|
|
|
<td>3 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Src1</td>
|
|
|
<td>3 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Src2</td>
|
|
|
<td>3 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>XXX</td>
|
|
|
<td>XXX</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
</li>
|
|
|
<li>This format is made of 16 bits (1 word) and it can be used to form the machine instruction corresponding to the ADD, SUB and MUL assembly instructions.</li>
|
|
|
<li>XXX -> these’s X’s can be either 0’s or 1’s – they are not used by the microproccesor.</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
<li>Format 2:
|
|
|
<ul>
|
|
|
<li>
|
|
|
<table>
|
|
|
<thead>
|
|
|
<tr>
|
|
|
<th>Label</th>
|
|
|
<th>Bits</th>
|
|
|
</tr>
|
|
|
</thead>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td>Opcode</td>
|
|
|
<td>4 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Dest</td>
|
|
|
<td>3 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>XXX</td>
|
|
|
<td>3 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>XXXXXX</td>
|
|
|
<td>6 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>padding</td>
|
|
|
<td>4 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Memory address of Src</td>
|
|
|
<td>12 bits</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
</li>
|
|
|
<li>This format is made of 32 bits (2 words) and it can be used to form the machine instuctions corresponding to the LOAD assembly instruction.</li>
|
|
|
<li>XXX, XXXXXX and XXXX (padding) -> These X’s can be either 0’s or 1’s – they are not used by the microproccesor.</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
<li>Format 3:
|
|
|
<ul>
|
|
|
<li>
|
|
|
<table>
|
|
|
<thead>
|
|
|
<tr>
|
|
|
<th>Label</th>
|
|
|
<th>Bits</th>
|
|
|
</tr>
|
|
|
</thead>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td>Opcode</td>
|
|
|
<td>4 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>XXX</td>
|
|
|
<td>3 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Src</td>
|
|
|
<td>3 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>XXXXXX</td>
|
|
|
<td>6 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>padding</td>
|
|
|
<td>3 bits</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Memory address of Dest</td>
|
|
|
<td>12 bits</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
</li>
|
|
|
<li>This format is made of 32 bits (2 words) and it can be used to form the machine instruction corresponding to the STORE assembly instruction.</li>
|
|
|
<li>XXX and XXXXXX -> these X’s can be either 0’s or 1’s – they are not used by the microprocessor.</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
</ul>
|
|
|
|
|
|
<p>When the microprocessor decodes the opcode for a LOAD instruction, it will
|
|
|
know where to find the field Dest and where to find the field Src in the
|
|
|
instruction itself (Dest -> the first field after the opcode in the first word of the
|
|
|
insruction and Src -> the memory address located in the least significant 12 bits
|
|
|
of the second word composing this instruction). It will also know to ignore all
|
|
|
other bits (X’s) in the instruction.</p>
|
|
|
|
|
|
<p>When the microprocessor decodes the opcode for a STORE instruction, it will
|
|
|
know where to find the field Src and where to find the field Dest in the
|
|
|
instruction itself (Src -> the second field after the opcode in the first word of the
|
|
|
insruction and Dest -> the memory address located in the least significant 12 bits
|
|
|
of the second word composing this instruction). It will also know to ignore all
|
|
|
other bits (X’s) in the instruction.</p>
|
|
|
|
|
|
<p>Note: About ISA design principles: When creating formats to encode instruction
|
|
|
set …</p>
|
|
|
|
|
|
<ul>
|
|
|
<li>As few of them as possible were created.</li>
|
|
|
<li>The fields that have the same purpose (such as Opcode, Dest and Src)
|
|
|
are placed in the same location in as many of the formats as possible.</li>
|
|
|
</ul>
|
|
|
|
|
|
<p>This helps simplify the design of the microprocessor (its datapath).
|
|
|
The bit patterns for the opcode are:</p>
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td>Opcode (instruction)</td>
|
|
|
<td>Bit pattern (4 bits)</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>padding</td>
|
|
|
<td>0000</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>ADD</td>
|
|
|
<td>0001</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>SUB</td>
|
|
|
<td>0010</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>MUL</td>
|
|
|
<td>0011</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>LOAD</td>
|
|
|
<td>1010</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>STORE</td>
|
|
|
<td>1011</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>…</td>
|
|
|
<td>…</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
<h3 id="b-description-of-x295-instruction-set">B. Description of x295+ instruction set</h3>
|
|
|
|
|
|
<table>
|
|
|
<thead>
|
|
|
<tr>
|
|
|
<th>C program</th>
|
|
|
<th>x295+ assembly program</th>
|
|
|
<th>x295+ machine code</th>
|
|
|
</tr>
|
|
|
</thead>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td><pre>z = (x + y) * (x - y);</pre></td>
|
|
|
<td>(empty)</td>
|
|
|
<td><pre>1010 000 XXX XXXXXX 0000 <Src 12 bits>
|
|
|
|
|
|
1010 001 XXX XXXXXX 0000 <Src 12 bits>
|
|
|
|
|
|
0001 010 000 001 XXX
|
|
|
|
|
|
0010 011 000 001 XXX
|
|
|
|
|
|
0011 100 010 011 XXX
|
|
|
|
|
|
1011 XXX 100 XXXXXX 0000 <Src 12 bits></pre></td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
<p>1) The first step in evaluating our x295+ instruction set is to translate the C program into</p>
|
|
|
|
|
|
<ul>
|
|
|
<li>an assembly program using the assembly instructions defined by our x295+
|
|
|
instruction set and</li>
|
|
|
<li>its corresponding machine code using the machine instructions defined by our
|
|
|
x295+ instruction set.</li>
|
|
|
</ul>
|
|
|
|
|
|
<p>For us to do: Our task is to complete the middle column (assembly code) in the table
|
|
|
above. The machine code has already been given. [3 marks]</p>
|
|
|
|
|
|
<p>2) The next step in evaluating our x295+ instruction set is to execute (hand trace) our
|
|
|
assembly program or its corresponding machine code and using the metric (criteria) called
|
|
|
memory traffic, we count the number of memory accesses our program makes during its
|
|
|
execution. In other words, we count how many time the execution of our program
|
|
|
required a word (16 bits) to be read from or written to memory.</p>
|
|
|
|
|
|
<p>For us to do: As part of this step in the evaluation of our x295+ instruction set, complete
|
|
|
the table below. [4 marks]</p>
|
|
|
|
|
|
<table>
|
|
|
<thead>
|
|
|
<tr>
|
|
|
<th>x295+ program (in assembly and machine code)</th>
|
|
|
<th>Fetch (number of word size memory accesses) + Provide an explaination explaining the count</th>
|
|
|
<th>Decode/Execute (number of word size memory accesses) + Provide an explaination explaining the count</th>
|
|
|
</tr>
|
|
|
</thead>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td>Assembly code: ____<br />
|
|
|
Machine code: <pre>1010 000 XXX XXXXXX 0000 <Src 12 bits></pre></td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaionation ____</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Assembly code: ____<br />
|
|
|
Machine code: <pre>1010 001 XXX XXXXXX 0000 <Src 12 bits></pre></td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Assembly code: ____<br />
|
|
|
Machine code: <pre>0001 010 000 001 XXX</pre></td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Assembly code: ____<br />
|
|
|
Machine code: <pre>0010 011 000 001 XXX</pre></td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Assembly code: ____<br />
|
|
|
Machine code: <pre>0011 100 010 011 XXX</pre></td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Assembly code: ____<br />
|
|
|
Machine code: <pre>1011 XXX 100 XXXXXX 0000 <Src 12 bits></pre></td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
<td>Count: ____<br />
|
|
|
Explaination: ____</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Grand total: ____</td>
|
|
|
<td>Total: ____</td>
|
|
|
<td>Total: ____</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
<p>3) We also evaluate our instruction set using the metric (criteria) called static code size. For
|
|
|
us to do: Fill in the blanks in the statement below: [0.5 marks]</p>
|
|
|
<ul>
|
|
|
<li>The code size of our x295+ program is <strong>__</strong><strong>__ instructions ( __</strong><strong>__</strong> words).</li>
|
|
|
</ul>
|
|
|
|
|
|
<h2 id="instruction-set-3--x295">Instruction Set 3 – x295++</h2>
|
|
|
|
|
|
<h3 id="a-description-of-x295-instruction-set-architecture-isa-2">A. Description of x295++ instruction set architecture (ISA)</h3>
|
|
|
|
|
|
<p>Would reducing the number of operands to the instructions in our instruction set decrease
|
|
|
the number of memory accesses the microprocessor does when fetching, decoding and
|
|
|
executing our program?</p>
|
|
|
|
|
|
<p>Would introducing another instruction, namely COPY, in our instruction set also decrease the
|
|
|
number of memory accesses the microprocessor does when fetching. decoding and executing
|
|
|
our program?</p>
|
|
|
|
|
|
<p>With the above two ideas in mind, we specified a third instruction set architecture (ISA) with
|
|
|
the same components as x295 and x295+, but with the following modifications:</p>
|
|
|
|
|
|
<ul>
|
|
|
<li>Instruction set (assembly and machine instructions)
|
|
|
<ul>
|
|
|
<li>Operand Model:
|
|
|
<ul>
|
|
|
<li>2 operand model</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
<li>Assembly instructions:
|
|
|
<ul>
|
|
|
<li><code class="language-plaintext highlighter-rouge">ADD rA,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- rA + rC</code></li>
|
|
|
<li><code class="language-plaintext highlighter-rouge">SUB rA,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- rA - rC</code></li>
|
|
|
<li><code class="language-plaintext highlighter-rouge">MUL rA,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- rA * rB</code></li>
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<li><code class="language-plaintext highlighter-rouge">COPY rA,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- rA</code></li>
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<li><code class="language-plaintext highlighter-rouge">LOAD a,rC</code>; meaning: <code class="language-plaintext highlighter-rouge">rC <- M[a]</code></li>
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<li><code class="language-plaintext highlighter-rouge">STORE rA,c</code>; meaning: <code class="language-plaintext highlighter-rouge">M[c] <- rA</code></li>
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</ul>
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</li>
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<li>Machine code formats:
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<ul>
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<li>Format 1:
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<ul>
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<li>
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<table>
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<thead>
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<tr>
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<th>Lablel</th>
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<th>Bits</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>Opcode</td>
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<td>4 bits</td>
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</tr>
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<tr>
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<td>Dest</td>
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<td>3 bits</td>
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</tr>
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<tr>
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<td>Src</td>
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<td>3 bits</td>
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</tr>
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<tr>
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<td>XXXXXX</td>
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<td>6 bits</td>
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</tr>
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</tbody>
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</table>
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</li>
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<li>This format is made of 16 bits (1 word) and it can be used to form the machine
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instructions corresponding to the ADD, SUB, MUL and COPY assembly instructions.</li>
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<li>XXXXXX -> these X’s can be either 0’s or 1’s.</li>
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<li>The bit patterns for the opcode are:
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|
Opcode (instruction)|Bit pattern (4 bits)
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|
—|—
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|
|
padding|0000
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|
|
ADD|0001
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|
|
SUB|0010
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|
|
MUL|0011
|
|
|
COPY|1001
|
|
|
LOAD|1010
|
|
|
STORE|1011
|
|
|
…|…</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
</ul>
|
|
|
</li>
|
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|
</ul>
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</li>
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</ul>
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|
|
|
<h3 id="b-evaluation-of-x295-instruction-set-1">B. Evaluation of x295++ instruction set</h3>
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td>C program</td>
|
|
|
<td>x295++ assembly program</td>
|
|
|
<td>x295++ machine code</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td><code class="language-plaintext highlighter-rouge">z = (x + y) * (x – y);</code></td>
|
|
|
<td> </td>
|
|
|
<td> </td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
<p>1) The first step in evaluating our x295++ instruction set is to translate the C program into</p>
|
|
|
<ul>
|
|
|
<li>an assembly program using the assembly instructions defined by our x295++
|
|
|
instruction set and</li>
|
|
|
<li>its corresponding machine code using the machine instructions defined by our
|
|
|
x295++ instruction set.</li>
|
|
|
<li>For us to do: Our task is to complete the middle column (assembly code) and the right
|
|
|
column (machine code) in the table above. [5 marks]
|
|
|
<ul>
|
|
|
<li>Challenge: Can you express your x295++ assembly program and machine code
|
|
|
with the fewest number of instructions. This may require you to first
|
|
|
readjust the above C program.</li>
|
|
|
</ul>
|
|
|
</li>
|
|
|
</ul>
|
|
|
|
|
|
<p>2) The next step in evaluating our x295++ instruction set is to execute (hand trace) our
|
|
|
assembly program or its corresponding machine code and using the metric (criteria) called
|
|
|
memory traffic, we count the number of memory accesses our program makes during its
|
|
|
execution. In other words, we count how many time the execution of our program
|
|
|
required a word (16 bits) to be read from or written to memory.</p>
|
|
|
|
|
|
<p>For us to do: As part of this step in the evaluation of our x295++ instruction set,
|
|
|
complete the table below. [4 marks]</p>
|
|
|
|
|
|
<table>
|
|
|
<thead>
|
|
|
<tr>
|
|
|
<th>x295++ program (in assembly and machine code)</th>
|
|
|
<th>Fetch (number of word size memory accesses) + Provide an explaination explaining the count</th>
|
|
|
<th>Decode/Execute (number of word size memory accesses) + Provide an explaination explainaing the count</th>
|
|
|
</tr>
|
|
|
</thead>
|
|
|
<tbody>
|
|
|
<tr>
|
|
|
<td colspan="3">... expand the table by adding as many rows as needed using the
|
|
|
row format seen in the tables above ...</td>
|
|
|
</tr>
|
|
|
<tr>
|
|
|
<td>Grand total: ____</td>
|
|
|
<td>Total: ____</td>
|
|
|
<td>Total: ____</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
<p>3) We also evaluate our instruction set using the metric (criteria) called static code size. For
|
|
|
us to do: Fill in the blanks in the statement below: [0.5 marks]</p>
|
|
|
<ul>
|
|
|
<li>The code size of our x295++ program is <strong>__</strong><strong>_ instructions ( __</strong>_____ words).</li>
|
|
|
</ul>
|
|
|
|
|
|
<h3 id="conclusion">Conclusion</h3>
|
|
|
|
|
|
<hr />
|
|
|
|
|
|
<p>For us to do: Considering the memory traffic metric (number of memory accesses required
|
|
|
by our test program), which instruction set (x295, x295+ or x295++) produces the most
|
|
|
time efficient program? [0.5 marks]</p>
|
|
|
|
|
|
<p>For us to do: Considering the static code size metric (number of instructions/words required
|
|
|
to implement our test program), which instruction set (x295, x295+ or x295++) produces
|
|
|
the smallest program? [0.5 marks]</p>
|
|
|
|
|
|
<hr />
|
|
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|
|
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<footer>
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|
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</footer>
|
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</div>
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</main>
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</body>
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</html>
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